Ultimately, this reduces the number of stages in the pipeline and allows more operations per CPU clock cycle, which improves performance and saves power at the same time. Micro-operations refer to low-level instructions used to implement more complex instructions, and a micro-op cache allows these instructions that come through the pipeline to be stored on it so they can be accessed more quickly the next time. Bulldozer lacked an operation cache, which meant it needed to fetch data from other caches to carry out even commonly used micro-operations. Instead, Zen's design now hews closer to Intel's, and each thread will register as a separate core.Īnother key change is the inclusion of something called a micro-op cache on Zen. This finally overcomes one of the key limitations of Bulldozer, where a shared floating point unit between two threads negatively impacted floating point performance. Intel's version of SMT is the by-now familiar HyperThreading, but you'll not catch anyone from AMD referring to their technology as such. Zen also marks the first time AMD is implementing simultaneous multi-threading (SMT) in a while, and each Zen core is now able to support two threads. However, we’re still missing details on what sort of interconnect it is using to link up the different CCXs. The amount of 元 cache would double in this case as well to a total of 16MB across two CCXs. In order to increase core counts, AMD connects multiple CCXs, for instance to create an 8-core (16 threads, 2 per core) SKU. All four cores have access to the entire 元 cache with the same average latency, but they each also have 512KB of private L2 cache. In addition, while we already know that AMD is claiming a 40 per cent jump in instructions per clock (IPC) compared to Excavator, a demonstration with the Blender rendering benchmark showed Zen’s IPC to actually be on par with Intel’s 14nm Broadwell-E Core i7-6900K.īroadly speaking, the improvements AMD made to the Zen architecture can be divided into three key areas – an upgraded core engine, better cache system, and lower power consumption.ĪMD also gave us a look at its Zen CPU core, where the CPU complex (CCX) comprises four cores connected to a central 16-way 8MB 元 cache that has been split into four slices. Zen is a “clean sheet” design, which means we’re finally leaving the Bulldozer architecture behind for good as AMD has built Zen from the ground up. This is the chip that will go head to head with Intel’s Kaby Lake processors next year, and is essentially AMD’s best shot at recapturing the enthusiast market. At this week’s Hot Chips conference, the chipmaker took a microscope to Zen’s architecture and unwrapped all the small details, following up on the broad strokes it had already revealed about at IDF in San Francisco. A broad overview of the improvements coming to AMD’s Zen microarchitectureĪMD has made good on its promise to unveil more details on its upcoming x86 Zen processors.
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